The inventors have examined the following techniques applicable to, for example, a clock recovery circuit.
FIG. 7 is diagram illustrating a PON (passive optical network) system according to the related art. The PON system is constructed by connecting an OLT (optical line terminal) 701 installed in the central office of a communication service provider and ONUs (optical network units) 702-n (n is a natural number) installed at plural user sites using an optical fiber 703 and a coupler 704 that branches the optical fiber.
Data signals are transmitted as a series of burst data signals from each of the ONUs 702-n to the OLT 701. FIG. 8 is a conceptual diagram illustrating upstream data transmission in the PON system. Each of the ONUs 702-n transmits a burst data signal 801-n during a time-division time slot. The burst data signal 801-n includes a preamble 802-n that is the head of the burst data signal detected by the OLT 701 to recover a clock and a payload 803-n that stores communication data of the user. The OLT 701 and the ONUs 702-n have their own internal clock generating sources, and each of the ONUs 702-n transmits a burst signal having a phase synchronized with the phase of its own internal clock. Therefore, the OLT 701 is provided with a clock recovery circuit that recovers a clock having the same phase as the burst data signal from the preamble 802-n whenever receiving the burst data signals 801-n from the ONUs 702-n. The period from the time when the clock recovery circuit detects the start of the transmission of burst data to the time when the clock recovery circuit recovers a clock having the same phase as the burst data signal is referred to as a bit synchronization period.
In the OLT having a long bit synchronization period, it is necessary to lengthen the preamble area. When the preamble area is lengthened, in the PON system in which each ONU transmits the burst data signal, the percentage of payload in the overall amount of communication is lowered, and data transmission efficiency is reduced. Therefore, a clock recovery circuit capable of having a short bit synchronization period is needed.
The clock recovery circuit needs to change the phase of a recovery clock signal according to an unavoidable slow change in the clock frequency of an internal clock generating source of the ONU provided at a transmitter side, that is, a change in the phase of the burst data signal caused by a clock wander.
However, there is a fluctuation in a rising edge time and a falling edge time of the waveform of a signal input to the OLT 701, that is, high-frequency jitter in the waveform, due to unavoidable high-frequency jitter of the internal clock generating source of the ONU and waveform distortion depending on a transmission code sequence, which is caused by attenuation characteristics depending on the signal frequency of the optical fiber 703 and the coupler 704. The clock recovery circuit needs to cancel the high-frequency jitter in an input waveform and recover a clock with low jitter. That is, the clock recovery circuit needs to have a high high-frequency jitter tolerance.
As described above, the clock recovery circuit for a burst transmission system, such as a PON system, needs to satisfy three requirements, that is, a short bit synchronization period, a clock wander tracking performance, and a high high-frequency jitter tolerance.
FIG. 9 is a diagram schematically illustrating the structure of a clock recovery circuit disclosed in JP-A-2004-180188. A phase difference detecting circuit 901 detects a phase difference between an input data signal 101 and a recovery clock (internal clock) 102, outputs an EARLY signal 902 when the phase of the recovery clock 102 leads the phase of the input data signal 101, and outputs a LATE signal 903 when the phase of the recovery clock 102 lags the phase of the input data signal 101. An averaging circuit 904 counts the EARLY signal 902 and the LATE signal 903, outputs a DOWN signal 906 when the number of EARLY signals is larger than the number of LATE signals, and outputs an UP signal 905 when the number of EARLY signals is smaller than the number of LATE signals. A clock phase adjusting circuit 907 changes the phase of a reference clock 908 input from the outside and outputs the recovery clock 102. The clock phase adjusting circuit 907 advances the phase of the internal clock when the UP signal 905 is input, and delays the phase of the internal clock when the DOWN signal 906 is input.
The clock recovery circuit disclosed in JP-A-2004-180188 adjusts the phase of the internal clock on the basis of a value obtained by averaging the phase difference between the input data signal 101 and the recovery clock 102 detected by the phase difference detecting circuit 901 using the averaging circuit 904. Therefore, high-frequency jitter included in the input data signal 101 is averaged and canceled, and there appears no high-frequency jitter in the recovery clock 102.
On the other hand, the clock wander with a low frequency included in the input data signal 101 is emphasized by the averaging operation. Therefore, the recovery clock 102 can follow the clock wander of the input data signal 101. In addition, the clock recovery circuit disclosed in JP-A-2004-180188 is not provided with a clock signal generating circuit, and adjusts the phase of the reference clock 908 input from the outside using the clock phase adjusting circuit 907, thereby adjusting the recovery clock 102. Therefore, it is possible to use the reference clock 908 with low jitter to reduce the jitter of the recovery clock. In this way, the clock recovery circuit disclosed in JP-A-2004-180188 satisfies a clock wander tracking performance and a high high-frequency jitter tolerance, among three requirements required for a clock recovery circuit for burst transmission.
However, the clock recovery circuit disclosed in JP-A-2004-180188 adjusts the phase of a clock on the basis of the average result of the phase difference between the input data signal 101 and the recovery clock 102 for a predetermined period of time. Therefore, it requires a long time to synchronize the phase of the input data signal 101 with the phase of the recovery clock 102. As a result, the clock recovery circuit disclosed in JP-A-2004-180188 has a problem in that the bit synchronization period is long.
FIG. 10 is a diagram schematically illustrating the structure of a clock recovery circuit disclosed in Masafumi Nogawa, et al., “A 10 Gb/s Burst-Mode CDR IC in 0.13 μm CMOS)”, 2005 IEEE International Solid-State Circuits Conference Digest of Technical Papers, February 2005, pp. 228 and 229. An internal clock generating circuit 1001 adjusts the frequency of a generated clock in response to a control signal 1003 transmitted from an internal clock frequency control circuit 1002. In this case, the internal clock frequency control circuit 1002 appropriately adjusts the control signal 1003 such that the code period of an input data signal 101 is synchronized with the period of a recovery clock 102. An edge detecting circuit 1004 detects a rising edge and a falling edge of the input data signal 101, and outputs an internal clock phase reset signal 1005 at the rising and falling edge timings. The internal clock generating circuit 1001 resets the phase of a generated clock in synchronization with the internal clock phase reset signal 1005. The internal clock generating circuit 1001 is generally formed by connecting even-numbered variable delay logic inverting circuits and one negative AND circuit in a ring shape. It is possible to change the frequency of a generated clock by adjusting the delay time of the variable delay logic inverting circuit. In addition, it is possible to reset the phase of the clock by inputting the internal clock phase reset signal 1005 to the negative AND circuit.
According to the clock recovery circuit disclosed in the above-mentioned paper, the phase of the recovery clock 102 is reset at the edge time of the input data signal 101. Therefore, it is possible to synchronize the phase of the recovery clock 102 with the phase of an input burst signal at the first rising edge from the start of burst transmission. In addition, the phase of the recovery clock is reset at the edge time of the input signal. Therefore, even when there is a clock wander in the input data signal 101, the phase of the recovery clock can follow the phase of the input data signal 101. In this way, the clock recovery circuit disclosed in the above-mentioned paper satisfies a short bit synchronization period and a clock wander tracking performance, among the above-mentioned three requirements required for a clock recovery circuit for burst transmission.
However, the clock recovery circuit disclosed in the above-mentioned paper directly resets the phase of the internal clock generating circuit 1001 at the edge time of the input data signal 101. Therefore, high-frequency jitter included in the input data signal 101 is transferred to the recovery clock. In addition, since the internal clock generating circuit 1001 needs to be provided in the clock recovery circuit, the size or the power consumption of the circuit is restricted, and it is difficult to form a clock generating circuit with low jitter. Therefore, the clock data generating circuit disclosed in the above-mentioned paper has a low high-frequency jitter tolerance.